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HT23B60
6011 Pixel Data Bank 8-Bit Mask MCU
Features
* Operating voltage range: 2.4V~5.5V * Program ROM: 32K16 bits * Data RAM: 2.3K8 bits * 16-bit table read instructions * Eight-level subroutine nesting * Timer - Two 16-bit programmable timer counters - Real time clock (RTC) - Watchdog Timer (WDT) * Four operating modes: Idle mode, Sleep mode, * Build-in Low Battery detector * 14 bidirectional I/O lines, 16 bidirectional I/O lines are
share pin with segments
* LCD driver: - Up to a max. of 60 segments and 11 common - 660 dots, 1/4 or 1/5 bias capability, 1/10 or 1/11
duty, R type
- LCD com/seg driving strength can be adjusted to
Green mode and Normal mode
* Built-in 32768Hz xtal oscillator circuit * Build-in circuit dual system clock 32768Hz, 3.58MHz
compromise the display quality and current consumption, adjustable 16-level VLCD - Segment 0~15 supports Key Scan function * Build-in a serial-parallel-interface hardware circuit
* Build-in a 8-bit PWM D/A hardware circuit * 100-pin QFP package
General Description
HT23B60 is an 8-bit CMOS microcontroller with various functionalities in a compact package such as SRAM, ROM I/Os, interrupt controller, timer and LCD controller/driver. Its suitable for use as electrical data bank, LCD game, calendar and speech products.
Block Diagram
RES P ro g ra m C o u n te r P ro g ra m ROM STA STA STA STA STA STA STA STA CK0 C K 1 3 2 7 6 8 H z IN T /P B 3 CK2 CK3 In te rru p t C ir c u it CK4 CK5 RTC CK6 IN T C CK7 TM R0 TM R0C TM R2 M U X
S Y S C L K /4 3 .5 8 M H z /4 32768H z M U X PW M1
In s tr u c tio n R e g is te r
PW MDAC1 MP0 MP1 M U X DATA M e m o ry TM R2C PFD M PW MDAC2
U X
PW M2
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r ACC
MUX
PA PAC PA0~PA7
STATUS
S h ifte r PB PBC PB0~PB5
X IN XOUT XC
OSC
C ir c u it 3 .5 8 M H z
LCD M e m o ry
W DTS W D T P r e s c a le r
VLCD COM0 COM1 COM9 CO M 10 SEG0 SEG1 SEG 58 SEG 59
32768H z W DT OSC S y s te m C lo c k /4 L B IN
LCD Dr 601 1 /4 , 1 /5 1 /1 0 , 1 /1 1 1
iv e r B ia s D u ty Low V o lta g e D e te c to r
SEG 0~15 K e y S c a n S tro b e
S e r ia l In te rfa c e
S C L K /P B 0 D I/P B 2 D O /P B 1
Rev. 1.10
1
March 1, 2004
HT23B60
Pin Assignment
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SE SE SE SE SE SE SE
32 31
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72
30 29 28 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 G9 G8 G7 G6 G5 G4 G3 27
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50
71 70 69 68
H T23B 60 1 0 0 Q F P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG SEG NC NC SEG SEG SEG SEG SEG COM COM COM COM COM COM COM COM COM COM COM NC VLC L B IN XC X IN XOU PW M PW M NC NC D
53 54 55 56 57 58 59 0 1 2 3 4 5 6 7 8 9 10
T 2 1
PB PB PB PB PB PB PA PA PA PA PA PA PA PA SE SE SE 2 1 0 5 G0 G1 G2 7 6 5 4 3 CLK O I T
GND VCC RES 0 /S 1 /D 2 /D 3 /IN 4
Rev. 1.10
2
March 1, 2004
HT23B60
Pad Assignment
SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 SEG 17 SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG4 SEG5 SEG6 SEG7 99 SEG8 98 SEG9
SEG3 1
102
101
100
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78 76
77 SEG 30 SEG 31 SEG 32 SEG 33 SEG 34 SEG 35 SEG 36 SEG 37 SEG 38 SEG 39 SEG 40 SEG 41 SEG 42 SEG 43 SEG 44 SEG 45 SEG 46 SEG 47 SEG 48 SEG 49 SEG 50 SEG 51 SEG 52 SEG 53 SEG 54 SEG 55
SEG2 2 3 4 5 6 7 8 9 SEG1 SEG0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB4 P B 3 /IN T P B 2 /D I P B 1 /D O P B 0 /S C L K RES VCC VCC GND
75 74 73 72 71 70 69 68 67 66 (0 ,0 ) 65 64 63 62 61 60 59 58 57 56 21 55 54 53 38 39 40 41 42 43 44 45 46 47 48 49 52 50 51 T R IM 2 T R IM 3 T R IM 4 T R IM 1 T R IM 0
10 11 12 13 14 15 16 17 18 19 20
22 28 23 24 25 26 27
29 30
31 32
33 34
35 36
37
X IN
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
XOUT
XC
PW M1
PW M2
CO M 10
SEG 59
SEG 58
SEG 57
SEG 56
L B IN
GND
* The IC substrate should be connected to VSS in the PCB layout artwork.
VLCD
Rev. 1.10
3
March 1, 2004
HT23B60
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 X -1348.345 -1334.345 -1334.345 -1334.345 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1330.600 -1323.500 -1282.800 -1323.500 -1323.500 -1191.900 -1083.800 -945.113 -835.109 -683.945 -519.280 -477.416 -425.640 -373.864 -312.995 -257.745 -207.745 -157.745 -107.745 -57.745 42.255 142.255 242.255 342.255 442.255 542.255 642.255 742.255 842.255 942.255 1042.255 1142.255 11314.745 Y 1337.600 1076.850 966.250 866.250 746.150 635.550 535.550 424.950 324.950 214.350 114.350 3.750 -96.250 -206.850 -306.850 -417.450 -517.450 -628.050 -729.826 -863.400 -970.900 -1110.150 -1305.950 -1307.450 -1307.450 -1293.950 -1293.950 -1217.385 -1153.900 -1321.600 -1153.900 -1321.600 -1153.860 -1320.790 -1153.861 -1320.790 -1153.821 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1320.790 -1352.900 Pad No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 X 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1314.745 1346.855 1246.855 1146.855 1046.855 946.855 846.855 746.855 646.855 546.855 446.855 346.855 246.855 146.855 46.855 -84.745 -184.745 -295.345 -395.345 -505.945 -605.945 -716.545 -816.545 -927.145 -1027.145 -1137.745 -1237.745 Y -1252.900 -1152.900 -1052.900 -952.900 -852.900 -752.900 -652.900 -552.900 -452.900 -352.900 -252.900 -152.900 -52.900 47.100 147.100 247.100 347.100 447.100 547.100 647.100 747.100 847.100 947.100 1047.100 1147.100 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1319.590 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 1337.600 Unit: mm
Rev. 1.10
4
March 1, 2004
HT23B60
Pad Description
Pad No. 4~1 Pad Name SEG0~3 I/O O Mask Option 3/4 Description Selectable as LCD segment signal output or keyscan strobe signal.
12~5
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as Wake-up wake-up input by mask option. Software instructions determine the or None CMOS output or Schmitt trigger input with or without pull-high register by register [35H]. 3/4 Bidirectional 2-bit input/output port Schmitt trigger input with or without pull-high register by software option or CMOS output Software instructions determine the bidirectional input/output pin or external interrupt Schmitt trigger input or CMOS output. When the [INTC0].1 is set to 1 the PB3 will used to external interrupt input pin. For I/O pin: Schmitt trigger input with or without pull-high register by software option or CMOS output For INT: Edge trigger activated on a falling edge.
14~13
PB4~PB5
I/O
15
PB3/INT
I/O
3/4
16
PB2/DI
Can be optioned as bidirectional input/output or serial data input. I/O Serial For I/O pin: Schmitt trigger input or CMOS output, see mask option or Data Input table for pull-high function I For serial data input: serial data input without pull-high resistor I/O or O Serial Data Output Can be optioned as bidirectional input/output or serial data output. For I/O pin: Schmitt trigger input or CMOS output, see mask option table for pull-high function For serial data output: SK is a CMOS output Can be optioned as bidirectional input/output or serial interface clock signal. For I/O pin: Schmitt trigger input with or without pull-high resistor by register [36H] or CMOS output For serial interface clock signal: Use as serial I/O interface clock signal SCLK should be set as serial clock output and after 8 clocks from the SCLK terminal, clock output is automatically suspended. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground Positive PWM CMOS output Negative PWM CMOS output A 32768Hz crystal (or resonator) should be connected to this pin and XIN A 32768Hz crystal (or resonator) should be connected to this pin and XOUT External low pass filter used for frequency up conversion circuit
17
PB1/DO
18
PB0/SCLK
I/O
SCLK Signal
19 20, 21 22, 23 24 25 26 27 28 29 31 33 35 37 30 32
RES VDD VSS PWM1 PWM2 XOUT XIN XC TRIM0 TRIM1 TRIM2 TRIM3 TRIM4 LBIN VLCD
I 3/4 3/4 O O O I I
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3/4
3/4
Test pin only
I I
3/4 3/4
This pin detects battery low through external R1/R2 to determine threshold, when the low voltage detect function is disabled, the LBIN pin should be connected to VDD. LCD voltage input
Rev. 1.10
5
March 1, 2004
HT23B60
Pad No. 46~38, 36 34 102~47 Pad Name COM0~8 COM9 COM10 SEG4~59 I/O Mask Option 3/4 3/4 LCD common signal output LCD segment signal output Description
O O
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V Input Voltage ............................ VSS-0.5V to VDD+0.5V Storage Temperature ...........................-55C to 150C Operating Temperature ..........................-10C to 70C
Current Drain Per Pin Excluding VDD and VSS ...................................................................................................10mA Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current (In Normal Mode) Test Conditions VDD Conditions
Ta=25C Min. Typ. Max. Unit 2.4 3/4 3.0 1 5.5 1.5 V mA
3/4 3V application 32768Hz on, 3.58MHz on, 3V CPU on, LCD on, WDT on, no load 32768Hz on, 3.58MHz off 3V CPU on, LCD off, WDT off, no load 32768Hz on, 3.58MHz off, 3V CPU off, LCD off, WDT off, no load 32768Hz off, 3.58MHz off, 3V CPU off, LCD off, WDT off, no load 3V 3V 3V 3V 3V VOL=0.3V 3V VOH=2.7V 3V VOL=0.3V 3V VOH=2.7V 3V VOL=0.3V 3V VOH=2.7V 3V 3V 3/4 3/4 3/4 3/4 3/4 3/4
IDD2
Operating Current (In Green Mode)
3/4
8
15
mA
ISTB1
Standby Current 1 (In Sleep Mode)
3/4
2.5
3
mA
ISTB2 VIL VIH VOL VOH IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH LBIN
Standby Current 2 (In Idle Mode) Input Low Voltage for I/O Port Input High Voltage for I/O Port Output Low Voltage Output High Voltage I/O Port Sink Current I/O Port Source Current Segment, Common Output Sink Current Segment, Common Output Source Current PWM Sink Current PWM Source Current Pull-high Resistance of I/O Ports Low Battery Detection Reference Voltage
3/4 0 2.0 3/4 2.3 8 -4 270
3/4 3/4 3/4 3/4 3/4 13 -8 480
1 1.0 VDD 0.4 VDD 3/4 3/4 3/4 3/4 3/4 3/4 90
mA V V V V mA mA mA mA mA mA kW V
-100 -140 16 -16 30 26 -26 60
1.10 1.15 1.20
Rev. 1.10
6
March 1, 2004
HT23B60
A.C. Characteristics
Symbol fSYS1 fSYS2 tSTB Parameter Operating System Clock (In Green Mode) Operating System Clock (In Normal Mode) Green Mode to Normal Mode System Frequency Stable Time Test Conditions VDD 3V 3V 3V 3V Conditions 3/4 3/4 3/4 3/4 Ta=25C Min. Typ. Max. Unit 3/4 3/4 3/4 45 23 3/4 3/4 1 3/4 1 32 3.58 3/4 90 45 512 15.6 3/4 1024 3/4 3/4 3/4 20 180 90 3/4 3/4 3/4 3/4 3/4 kHz MHz ms ms ms tSYS ms ms tSYS ms
tWDTOSC1 Watchdog Oscillator Period tWDTOSC2 Watchdog Time-out Period (WDT OSC) tWDT2 tWDT3 tRESET tSST tINT Watchdog Time-out Period (System Clock) Watchdog Time-out Period (32kHz OSC) RESET Input Pulse Width System Start-up timer Period Interrupt Pulse Width
3V Without WDT prescaler 3V Without WDT prescaler 3V Without WDT prescaler 3/4 3/4 3/4 3/4 3/4 3/4
Rev. 1.10
7
March 1, 2004
HT23B60
Functional Description
Execution Flow The system clock for the HT23B60 is derived from a 32768Hz crystal oscillator. A built-in frequency up conversion circuit provides dual system clock, namely 32768Hz and 3.58MHz. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.
T1 S y s te m O S C 2 (R C C lo c k o n ly ) PC
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4 1 3 b its P ro g ra m C o u n te r
B ank0
B ank1 B ank2 819216 B its 4000H 5FFFH 6000H 7FFFH
PC
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
PC+1
PC+2 S ta c k
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
0000H 1FFFH
2000H 3FFFH
B ank3
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
B a n k P o in te r R e g is te r B it6 ,B it5
A 1 4 ,A 1 3 B u ffe r
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n 3 2 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution Flow Program ROM Address *14 0 0 0 0 0 0 0 *13 0 0 0 0 0 0 0 *12 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 0 *10 0 0 0 0 0 0 0 *9 0 0 0 0 0 0 0 *8 0 0 0 0 0 0 0 *7 0 0 0 0 0 0 0 PC+2 *14 *13 *12 *11 *10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *6 0 0 0 0 0 0 0 *5 0 0 0 0 0 0 0 *4 0 0 0 0 1 1 1 *3 0 0 1 1 0 0 1 *2 0 1 0 1 0 1 0 *1 0 0 0 0 0 0 0 *0 0 0 0 0 0 0 0
Mode Initial Reset External or Serial Input Interrupt Timer Counter 0 Overflow Timer Counter 2 Overflow Keyscan Overflow RTC Overflow PWM Interrupt Skip Loading PCL Jump, Call Branch Return from subroutine
BP.6 BP.5 #12 #11 #10 S14 S13 S12 S11 S10
Program ROM Address Note: *14~*0: Program ROM address @7~@0: PCL bits #12~#0: Instruction code bits S14~S0: Stack register bits BP.5, BP.6: Bit 5, 6 of bank pointer (04H)
Rev. 1.10
8
March 1, 2004
HT23B60
The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory - ROM The program memory, which contains executable program instructions, data and table information, is composed of a 3276816 bit format. However as the PC (program counter) is comprised of only 13 bits, the remaining 2 ROM address bits are managed by dividing the program memory into 4 banks, each bank having a range between 0000H and 1FFFH. To move from the present ROM bank to a different ROM bank, the higher 2 bits of the ROM address are set by the BP (Bank Pointer), while the remaining 13 bits of the PC are set in the usual way by executing the appropriate jump or call instruction. As the full 15 address bits are latched during the execution of a call or jump instruction, the correct value of the BP must first be setup before a jump or call is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank the program is in the program will always jump to the appropriate interrupt service address in Bank 0. The original full 15 bit address will be stored on the stack and restored when the relevant RET/RETI instruction is executed, automatically returning the program to the original ROM bank. This eliminates the need for programmers to manage the BP when interrupts occur. Certain locations in Bank 0 of program memory are reserved for special usage:
* ROM Bank 0 (BP5~BP6=00B)
0000H 0004H 0008H 000CH 0010H 0014H 0018H 0020H RTC PW M D e v ic e In itia liz a tio n P r o g r a m E x te r n a l o r S e r ia l In p u t In te r r u p t S u b r o u tin e T im e r C o u n te r 0 In te r r u p t S u b r o u tin e T im e r 2 In te r r u p t S u b r o u tin e K e y s c a n In te rru p t In te r r u p t S u b r o u tin e D /A In te r r u p t S u b r o u tin e P ro g ra m ROM
7FFFH 1 6 b its
Program Memory
* Location 00CH
This area is reserved for the timer 2 interrupt service program. If a timer interrupt resulting from a timer 2 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution.
* Location 010H
This area is reserved for the keyscan interrupt When the keyscan function is enabled and the stack is not full, the program begins execution a location 010H on each common clock.
* Location 014H
This location is reserved for real time clock (RTC) interrupt service program. When the RTC generator is enabled and time-out occurs, the RTC interrupt is enabled and the stack is not full, the program begins execution at location 014H.
* Location 018H
The ROM bank 0 ranges from 0000H to 1FFFH.
* Location 000H
This area is reserved for the initialization program. After a chip reset, the program always begins execution at location 000H.
* Location 004H
This area is reserved for the PWM D/A buffer empty interrupt service program. After the system latch a D/A code at RAM address 28H, if the interrupt is enabled and the stack is not full, the program begins execution at location 018H.
* Location 020H
For best condition, this location is reserved at the beginning when writing a program.
* ROM Bank 1~3 (BP5~BP6=01B~11B)
This area is reserved for the external interrupt or serial input interrupt service routine. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
* Location 008H
The range of the ROM starts from n000H to (n+1) FFFH. (n=2,4,6)
* Table location
This area is reserved for the timer counter 0 interrupt service program. If a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution. Rev. 1.10 9
Any location in the ROM space can be used as look up table. The instructions TABRDC [m] (use for any bank) and TABRDL [m] (only used for last page of program ROM) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is March 1, 2004
HT23B60
well-defined, the higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBHP, TBLP) is a read/write register (1FH, 07H), used to indicate the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. If this happens, errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupts should be disabled prior to the table read instruction. It should not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon requirements. Stack Register - STACK This is a special part of memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data Memory - RAM The data memory is designed with (19212)8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory. Most are read/write, but some are read only.
* Bank 0 (BP4~BP0=0000H)
The Bank 0 data memory includes special purpose and general purpose memory. The special purpose memory is addressed from 00H to 3FH. The special function registers include the indirect addressing registers (IAR0:00H, IAR1:02H), timer counter 0 higher order byte register (TMR0H: 0CH), timer counter 0 lower order byte register (TMR0L: 0DH), timer counter 0 control register (TMR0C: 0EH), timer 2 lower-order byte register (TMR2L:2BH), timer 2 higher-order byte register (TMR2H:2AH), timer 2 control register (TMR2C:2CH), real timer clock control register (RTC: 24H), program counter lower-order byte register (PCL: 06H), memory pointer registers (MP0: 01H, MP1:03H), accumulator (ACC:05H), table pointer lower-order byte register (TBLP: 07H), table pointer higher-order byte register (TBHP:1FH), table higher-order byte register(TBLH:08H), status register (STATUS:0AH), interrupt control register 0 ( I N T C 0 : 0 B H ) , i n t e r r u p t co n t r o l r e g i st e r 1 (INTC1:1EH), watchdog timer option setting register (WDTS:09H), PLL control register (OPMODE:26H), LCD control register (LCDC:2DH), LCD bright control register (VLCDC:34H), LCD segment output port 0 data register (LCDPC: 37H), LCD segment output port 0 control register (LCDPCC: 38H), LCD segment output port 1 data register (LCDPD:39H), LCD segment output port 1 control register (LCDPDC:3AH), PFD control register (PFDC:2FH), PWM data register (PWM:31H), PWM control register (PWMC:30H), serial data register (SRD:33H), serial control register (SRC:32H), I/O registers (PA:12H, PB:14H) , I/O control registers (PAC:13H, PBC:15H) and pull-high control register (PAPHC:35H, PBPHC:36H). The general purpose data memory, addressed from 40H to FFH, is used for data and control information under instruction commands. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible
Instruction TABRDC [m] TABRDL [m]
Table Location *14 #6 1 *13 #5 1 *12 #4 1 *11 #3 1 *10 #2 1 *9 #1 1 *8 #0 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table Location Note: @7~@0: TBLP register bit7~bit0 #6~#0: TBHP register bit6~bit0 *14~*0: Current program ROM table address bit14~bit0
Rev. 1.10
10
March 1, 2004
HT23B60
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3FH 40H FFH 40H FFH 40H FFH 80H FBH TM R2H TM R2L TM R2C LCDC PFDC PW MC PW M SRC SRD VLCD C PAPHC PBPHC LCDPC LCDPCC LCDPD LCDPDC LCD T im e r C o u n te r 2 H ig h e r - o r d e r B y te R e g is te r T im e r C o u n te r 2 L o w e r - o r d e r B y te R e g is te r T im e r C o u n te r 2 C o n tr o l R e g is te r LCD D r iv e r C o n tr o l R e g is te r PFD PW M PW M C o n tr o l R e g is te r C o n tr o l R e g is te r D a ta R e g is te r RTC OPMODE R e a l T im e C lo c k C o n tr o l R e g is te r O P M o d e ( P L L C o n tr o l) IN T C 1 TBHP In te r r u p t C o n tr o l B y te R e g is te r 1 T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r S p e c ia l P u r p o s e D a ta M e m o ry PA PAC PB PBC P A I/O P A I/O P B I/O P B I/O D a ta R e g is te r C o n tr o l R e g is te r D a ta R e g is te r C o n tr o l R e g is te r
IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R 0H TM R 0L TM R 0C
In d ir e c t A d d r e s s in g R e g is te r 0 M e m o r y P o in te r 0 In d ir e c t A d d r e s s in g R e g is te r 1 M e m o r y P o in te r 1 B a n k P o in te r A c c u m u la to r P ro g ra m C o u n te r L o w e r - b y te R e g is te r T a b le P o in te r L o w e r - o r d e r B y te R e g is te r T a b le H ig h e r - o r d e r B y te R e g is te r W a tc h d o g T im e r O p tio n S e ttin g R e g is te r S ta tu s R e g is te r In te r r u p t C o n tr o l R e g is te r 0 T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 C o n tr o l R e g is te r
through the memory pointer registers (MP0;01H, MP1;03H).
* Bank 1~11(BP4~PB0=0001B~1011B)
The range of RAM starting from 40H to FFH are for general purpose. Only MP1 can deal with the memory of this range.
* Bank 15 (BP4~BP0=1111B)
The range of RAM starts from 80H to FBH (BCH~BFH cant be used). Every bit stands for one dot on the LCD. If the bit is 1, the light of the dot on the LCD will be turned on. If the bit is 0, then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COMMON, and SEGMENT is as follows. LCD Driver Output The maximum output number of the HT23B60 LCD driver is 1160. The Common output signal can be selected as 11 com or 10 com and 1/4 or 1/5 bias by mask option. The LCD driver used the voltage of VLCD pin to the power source. To adjust the view angle, the programmer can select the real LCD power by the register 34H. Some of the Segment outputs share pins with keyscan outputs (seg0~15). Whether segment output or keyscan outputs can be determined by software option. LCD driver output can be enabled or disabled by setting the LCD (bit7 of LCDC; 2DH) without the influence of the related memory condition. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COMMON and SEGMENT is as follows: Register Label Bits R/W 3/4 LVEN 3/4
:U nused
Function
S e r ia l C o n tr o l R e g is te r S e r ia l D a ta R e g is te r B r ig h t C o n tr o l R e g is te r P o r t A P u ll- h ig h C o n tr o l R e g is te r P o r t B P u ll- h ig h C o n tr o l R e g is te r S e g m e n t O u tp u t P o r t 0 D a ta R e g is te r S e g m e n t O u tp u t P o r t 0 C o n tr o l R e g is te r S e g m e n t O u tp u t P o r t 1 D a ta R e g is te r S e g m e n t O u tp u t P o r t 1 C o n tr o l R e g is te r
0~1 RO Unused bit, read as 0 2 3 To enable/disable the low RW voltage detection function (0: disable; 1: enable) R Unused bit, read as 0
G e n e ra l P u rp o s e B a n k 0 D a ta M e m o ry (1 9 2 B y te ) G e n e ra l P u rp o s e B a n k 1 D a ta M e m o ry (1 9 2 B y te )
LCDC (2DH)
LVFG
4
1: LBIN pin voltage is less than low voltage detection level RO 0: LBIN voltage is not less than low voltage detection level R Unused bit, read as 0
G e n e ra l P u rp o s e B a n k 1 1 D a ta M e m o ry (1 9 2 B y te )
3/4 LCDON
5, 6 7
B a n k 1 5 D a ta M e m o ry (1 2 0 B y te )
To enable/disable the RW LCD output (0: disable; 1: enable)
RAM Mapping
LCDC Register
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VLCDC register (34H) LCD Level 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Bit7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.66VLCD 0.68VLCD 0.70VLCD 0.72VLCD 0.74VLCD 0.77VLCD 0.80VLCD 0.83VLCD 0.86VLCD 0.88VLCD 0.90VLCD 0.92VLCD 0.94VLCD 0.96VLCD 0.98VLCD 1.00VLCD
Note: VLCD=2.4V~5.5V The range of RAM starts from 80H to FBH Address 80H COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 C1H C2H C3H C4H C5H C6H - - - F5H F6H F7H F8H F9H FAH FBH 81H 82H 83H 84H 85H 86H- - - - B4H B5H B6H B8H B9H BAH BBH
Address C0H COM8 COM9 COM10 Bit0 Bit1 Bit2
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6-SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 LCD Display Memory: (Bank15) Note: C0~FB, bit3~7, R=0 BCH~BFH, R=0; FC~FFH, R=0 1: LCD pixels on 0: LCD pixels off
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HT23B60
An example of an LCD driving waveform is shown below: 1/11 duty, 1/5 bias
4 6 .5 4 H z 1 1024H z VD VD VD VD VD GN D D D D D D D D VD VD VD VD VD GN D D D D 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 1 2 3
COM0
4 /5 3 /5 2 /5 1 /5
COM1
4 /5 3 /5 2 /5 1 /5
SEG0
4 /5 3 /5 2 /5 1 /5
VDD VDD VDD VDD VDD GND
1/10 duty, 1/5 bias
5 1 .2 H z 1 1024H z VD VD VD VD VD GN D D VD VD VD VD VD GN D D D D D D D D D D 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3
COM0
4 /5 3 /5 2 /5 1 /5
COM1
4 /5 3 /5 2 /5 1 /5
SEG0
4 /5 3 /5 2 /5 1 /5
VDD VDD VDD VDD VDD GND
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HT23B60
1/11 duty, 1/4 bias
4 6 .5 4 H z 1 1024H z 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 1 2 3
COM0
3 /4 V 2 /4 V 1 /4 V G
VDD DD DD DD ND DD DD DD DD ND
COM1
V 3 /4 V 2 /4 V 1 /4 V G
SEG0
3 /4 V 2 /4 V 1 /4 V G
VDD DD DD DD ND
1/10 duty, 1/4 bias
5 1 .2 H z 1 1024H z 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3
COM0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
COM1
SEG0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
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HT23B60
Indirect Addressing Register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H, while writing to it results in no operation. The data movement function between two indirect addressing registers is not supported. The memory pointer registers MP0 and MP1, are 8-bit registers used to access the data memory by combining corresponding indirect addressing registers, Bank1~Bank11 and Bank15 can use MP1 only. Accumulator The accumulator is closely related to ALU operations. It is mapped to location 05H of the data memory and can also operate with immediate data. The data movement between two data memory must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PDF flags. In addition, operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by a system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status register are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Interrupt The HT23B60 provides external and a D/A interrupt and internal timer counter interrupts. The interrupt control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter and A14~A13 bits onto the Function
The ALU not only saves the results of a data operation but can also change the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Register Labels C Bits 0
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. It is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0
AC Z STATUS (0AH) OV PDF TO 3/4
1 2 3 4 5 6,7
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HT23B60
stack and then branching to subroutines at specified locations in the program memory. Only the program counter are pushed and A14~A13 bits onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service program which corrupt the desired control sequence, the contents must be saved first. External interrupt is triggered by a high to low transition of INT which sets the related interrupt request flag (EIF; bit 4 of INTC0). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt request flag (T0F; bit 5 of INTC0), caused by a timer counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The timer counter 2 interrupt is operated in the same manner as Timer counter 0. The related interrupt control bits ET2I and T2F of timer counter 2 are bit 3 and bit 6 of INTC0 respectively. The real time clock interrupt is generated by a 2Hz RTC generator. When the RTC time-out occurs, the interrupt request flag RTCF will be set. When the RTC interrupt is enabled, the stack is not full and the RTCF is set, a subroutine call to location 14H will occur. The interrupt request flag RTCF and EMI bits will be cleared to disable other interrupts. The keyscan interrupt is generated by LCD enable function. When the bit7 of the LCDC (2DH) is set 1, for every frame, each have a common signal all of which can generate a single interrupt. And the keyscan function have to be completed in the period of interrupt time. Register Label EMI EEI ET0I INTC0 (0BH) ET2I EIF T0F T2F 3/4 Bit No. 0 1 2 3 4 5 6 7 During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External interrupt Timer counter 0 overflow Timer counter 2 overflow Keyscan interrupt RTC interrupt PWM D/A interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
EMI, EEI, ET0I, ET2I, EKSI, ERTCI, EPWMI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (EIF, T0F, T2F, KSF, RTCF, PWMF) are set by hardware or software, they will remain in the INTC0 or INTC1 registers until the interrupts are serviced or cleared by a software instruction. It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt enable is not well controlled, once a CALL subroutine, if used in the interrupt subroutine, will corrupt the original control sequence.
Function Master (Global) interrupt (1=enable; 0=disable) External interrupt (1=enable; 0=disable) Timer counter 0 interrupt (1=enable; 0=disable) Timer counter 2 interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) Internal timer counter 0 request flag. (1=active; 0=inactive) Internal timer counter 2 request flag. (1=active; 0=inactive) Unused bit, read as 0
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INTCH register
HT23B60
Register Label EKSI ERTCI EPWMI INTC1 (1EH) 3/4 KSF RTCF PWMF 3/4 Bit No. 0 1 2 3 4 5 6 7 Function Controls the keyscan interrupt. (1=enable; 0=disable) Controls the RTC interrupt. (1=enable; 0=disable) PWM D/A interrupt (1=enable; 0=disable) Should be set 0 always. Keyscan interrupt request flag. (1=active; 0=inactive) RTC interrupt request flag. (1=active; 0=inactive) PWM D/A flag (1=enable; 0=disable) Should be set 0 always.
Oscillator Configuration There are two oscillator circuits in the controller, the external 32768Hz crystal oscillator and internal WDT RC oscillator. The 32768Hz crystal oscillator and frequency-up conversion circuit (32768Hz to 3.58MHz) are designed for dual system clock source. It is necessary for the frequency conversion circuit to add external RC components to make up the low pass filter that stabilize the output frequency 3.58MHz (see the oscillator circuit). The WDT RC oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the Idle mode (the system clock is stopped), the WDT RC oscillator still works within a period of 65ms~78ms. When the WDT is disabled or the WDT source is not this RC oscillator, the WDT RC oscillator will be disabled.
X1 X2 XC 32768
Watchdog Timer - WDT The WDT clock source is implemented by a WDT OSC or external 32768Hz or an instruction clock (system clock divided by 4), determined by mask option. This timer is designed to prevent software malfunction or protect the sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. If the device operates in a noisy environment, using the on-chip WDT OSC or 32768Hz crystal oscillator is strongly recommended. When the WDT clock source is selected, it will be first divided by 512 (9-stage) to get the nominal time-out period. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 can give different time-out periods. The WDT OSC period is 78ms. This time-out period may vary with temperature, VDD and process variations. The WDT OSC always works for any operation mode.
50nF
15kW 3nF
System Oscillator Circuit
If the instruction clock is selected as the WDT clock source, the WDT operates in the same manner except in the Sleep mode or Idle mode. In these two modes, the WDT stops counting and lose its protecting purpose. In this situation the logic can only be re-started by external logic.
Register
Label
Bits
R/W
Function Watchdog Timer division ratio selection bits Bit 2, 1, 0=000, Division ratio=1:1 Bit 2, 1, 0=001, Division ratio=1:2 Bit 2, 1, 0=010, Division ratio=1:4 Bit 2, 1, 0=011, Division ratio=1:8 Bit 2, 1, 0=100, Division ratio=1:16 Bit 2, 1, 0=101, Division ratio=1:32 Bit 2, 1, 0=110, Division ratio=1:64 Bit 2, 1, 0=111, Division ratio=1:128 Unused bit. These bits are read/write-able.
WDTS (09H)
WS0 WS1 WS2
0 1 2
RW
3/4
7~3
RW
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32768H z W DT OSC S y s te m C lo c k /4 M ask O p tio n S e le c t
W D T P r e s c a le r 9 - b it C o u n te r 7 - b it C o u n te r
W S0~W S2
8 -to -1 M U X W D T T im e - o u t
Watchdog Timer
The high nibble and bit3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status. The WDT time-out under Normal mode or Green mode will initialize chip reset and set the status bit TO. But in the Sleep mode or Idle mode, the time-out will initialize a warm reset and only the program counter and stack pointer are reset to 0. To clear the WDT contents (including the WDT prescaler), three methods are adopted; external reset (a low level to RES pin), software instruction and HALT instruction. The software instruction include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the mask option WDT instr. If the CLR WDT is selected (i.e. One clear instruction), any execution of the CLR WDT instruction will clear the WDT. In the case wherein CLR WDT1 and CLR WDT2 are chosen (i.e. two clear instructions), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Register Label 3/4 PLLEN OPMODE (26H) MODE0 MODE1 Bits 4~0 5 6 7 R/W RO RW RW RW
Controller Operation Mode Data bank controllers support two system clocks and four operation modes. The system clock could be 32768Hz or 3.58MHz and the operation mode could be Normal, Green, Sleep or Idle mode. There are all selected by the software. The following conditions will force the operation mode to change to Green mode: * Any reset condition from any operation mode
* Any interrupt from Sleep mode or Idle mode * A falling edge on any pin of Port A from Sleep mode or
Idle mode How to change the Operation Mode
* Normal mode to Green mode:
Step 1: Clear MODE1 to 0 After step 1, operation mode is changed to Green mode but the PLLEN status has no change. However, PLLEN can be cleared by software.
Function Unused bit, read as 0 1: Enable the frequency up conversion function to generate 3.58MHz 0: Disable the frequency up conversion function to generate 3.58MHz 0: Enable the 32768Hz oscillator while the HALT instruction is executed 1: Disable the 32768Hz oscillator while the HALT instruction is executed 1: Select 3.58MHz as CPU system clock 0: Select 32768Hz as CPU system clock
Operation Mode Description HALT Instruction Not Execute Not Execute Executed Executed MODE1 1 0 0 0 MODE0 X X 0 1 PLLEN 1 0 0 0 Operation Mode Normal Green Sleep Idle 32768Hz ON ON ON OFF 3.58MHz ON OFF OFF OFF System Clock 3.58MHz 32768Hz HALT HALT
Note: X means dont care
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* Normal mode or Green mode to Sleep mode:
Step 1: Clear MODE0 to 0 Step 2: Execute the HALT instruction After Step 2, the operation mode is changed to Sleep mode, the PLLEN and MODE1 are cleared to 0 by hardware. * Normal mode or Green mode to Idle mode: Step 1: Set MODE0 to 1 Step 2: Execute the HALT instruction After Step 2, the operation mode is changed to Idle mode, the PLLEN and MODE1 are cleared to 0 by hardware. * Green mode to Normal mode: Step 1: Set PLLEN to 1 Step 2*: Software delay 2ms at least Step 3: Set MODE1 to 1 After Step 3, operation mode is changed to Normal mode. Note: * Must delay 20ms at least, if you want to use stable clock source
(M H z ) 3 .5 8 V
DD
can be independently selected to wake-up the device by mask option. Awakening from Port A stimulus, the program will resume execution of the next instruction. The interrupts from the Sleep mode or Idle mode may cause two sequences to occur in the controller. One is if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. The other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. It is necessary to mention that if an interrupt request flag is set to 1 before entering the Sleep mode or Idle mode, the wake-up function of the related interrupt will be disabled. Once Idle mode wake-up event occurs, it will take 1024 system clock period or SST delay time to resume to Green mode. In this case, a dummy period is inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is completed. To minimize power consumption, all the I/O pins should be carefully managed before entering the Sleep mode or Idle mode. The Sleep mode or Idle mode is initialized by the HALT instruction and results in the following.
* The system clock will be turned off * The WDT function will be disabled if the WDT clock
=3V
0
2
4
6
8 1 0 1 2 1 4 1 6 1 8 2 0 (m s )
* Sleep mode or Idle mode to Green mode:
source is the instruction clock
* The WDT function will be disabled if the WDT clock
Method 1: Any reset condition occurred Method 2: Any interrupt is active Method 3: A falling edge on any pin of Port A After any source of the above descriptions, operation mode is changed to Green mode. The reset conditions include power on reset, external reset, WDT time-out reset. By examining the processor status flags, PDF and TO, the program can distinguish between different reset conditions. Refer to the Reset function for detailed description. A falling edge on port A and interrupt can be considered as a continuation of normal execution. Each bit in port A
source is the 32768Hz in Idle mode
* The WDT will still function if the WDT clock source is
the WDT OSC
* If the WDT function is still enabled, the WDT counter
and WDT prescaler will be cleared and recounted again * The contents of the on chip RAM and registers remain unchanged
* All the I/O ports maintain their original status * The PDF flag is set and the TO flag is cleared by hard-
ware.
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Reset There are three ways in which a reset can occur.
* Power on reset * A low pulse onto RES pin * time-out
To guarantee that the system oscillator is started and stabilized, the System Start-up Timer or SST provides an extra-delay of 1024 system clock pulses when the system is reset or awakes from the Sleep or Idle operation mode. By examining the processor status flags PD and TO, the software program can distinguish between the different chip resets. TO 0 PD 0 u 1 u 1 Reset Condition Power on reset External reset during Normal mode or Green mode External reset during Sleep mode or Idle mode WDT time-out during Normal mode or Green mode WDT time-out during Sleep mode or Idle mode
After these reset conditions, the Program Counter and Stack Pointer will be cleared to 0.
V
DD
100kW RES 0 .1 m F
u 0
Reset Circuit
1 1
HALT W DT W D T tim e - o u t
W a rm
R eset
Note: u stands for unchanged The functional unit chip reset status are shown below:
E x te rn a l
RES SST 1 0 - b it R ip p le C o u n te r
C o ld R e s e t
Program Counter Interrupt Prescaler
000H Disabled Cleared Cleared After a master reset, WDT begins counting (if the WDT function is enabled by mask option) Off Input mode Points to the top of the stack Disable
SYSCLK
Reset Configuration WDT
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Timer Counter 2 Input/output Port Stack Pointer
Reset Timing Chart
LCD Display
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HT23B60
When the reset conditions occurred, some registers may be changed or unchanged. Reset Conditions Register IAR0 MP0 IAR1 MP1 BP ACC PCL TBLP TBLH WDTS STATUS INTC0 TMR0H TMR0L TMR0C PA PAC PB PBC INTC1 TBHP RTC OPMODE TMR2H TMR2L TMR2C LCDC PFDC PWMC PWM SRC SRD VLCD PAPHC PBPHC LCDPC LCDPCC LCDPD LCDPDC Addr. 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 12H 13H 14H 15H 1EH 1FH 24H 26H 2AH 2BH 2CH 2DH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH Power On xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx 0000 0000 xxxx xxxx xxxx xxxx 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 -000 xxxx xxxx 0000 0000 0100 0000 xxxx xxxx xxxx xxxx 0000 1000 0000 0000 0000 0000 1111 1111 xxxx xxxx 0001 0000 0000 0000 0000 0000 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 1111 1111 x RES Pin uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 -000 uuuu uuuu u0u0 0000 01u0 0000 uuuu uuuu uuuu uuuu 0000 1000 0000 0000 0000 0000 1111 1111 uuuu uuuu 0001 0000 0000 0000 0000 0000 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 1111 1111 u RES Pin (Sleep/Idle) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 0000 -000 uuuu uuuu u0u0 0000 01u0 0000 uuuu uuuu uuuu uuuu 0000 1000 0000 0000 0000 0000 1111 1111 uuuu uuuu 0001 0000 0000 0000 0000 0000 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 1111 1111 u WDT uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu 0000 0000 uuuu uuuu uuuu uuuu 0000 1000 1111 1111 1111 1111 1111 1111 1111 1111 -000 -000 uuuu uuuu u0u0 0000 01u0 0000 uuuu uuuu uuuu uuuu 0000 1000 0000 0000 0000 0000 1111 1111 uuuu uuuu 0001 0000 0000 0000 0000 0000 1111 1111 0011 1111 1111 1111 1111 1111 1111 1111 1111 1111 u WDT (Sleep/Idle) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uu0u u000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu 0uuu uuuu uuuu u0u0 0000 01u0 0000 uuuu uuuu uuuu uuuu uu0u u000 u00u 0u00 uuuu uu00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 00uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u
RAM (Data & LCD) Note:
u stands for unchanged x stands for unknown - stands for unused
Rev. 1.10
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HT23B60
Timer 0
D a ta B u s T im e r C o u n te r 0 P r e lo a d R e g is te r R e lo a d
If the timer counter starts counting, it will count from the current contents in the timer counter to FFFFH. Once an overflow occurs, the counter is reloaded from the timer counter preload register and at the same time generates the corresponding interrupt request flag (T0F; bit of the INTC0). To enable the counting operation, the Timer ON bit (TON; bit 4 of the TMR0C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I can disable the corresponding interrupt service. In the case of timer counter OFF condition, writing data to the timer counter preload register will also reload that data to the timer counter. But if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. The timer counter will still operate until overflow occurs. When the timer counter (reading TMR0H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be taken into consideration by the programmer. Timer 2 The Timer 2 contains 16-bit programmable count-up counters whose clock may come from the 32768 Hz oscillator or the clock source come from the system clock divided by 4. There are three registers related to the timer counter 2; TMR2H (2AH), TMR2L (2BH), TMR2C(2CH). Writing TMR2L only writes the data into a low byte buffer, and writing TMR2H will simultaneously write the data and the contents of the low byte buffer into the timer 2 preload register (16-bit). The timer 2 preload register is changed by writing TMR2H operations and writing Function
S Y S C L K /4
T im e r C o u n te r 0
O v e r flo w to In te rru p t
L o w B y te B u ffe r
The timer 0 contains 16-bit programmable count-up counters and the clock source come from the system clock divided by 4. There are three registers related to the timer counter 0; TMR0H (0CH), TMR0L (0DH), TMR0C(0EH). Writing TMR0L only writes the data into a low byte buffer, and writing TMR0H will simultaneously write the data and the contents of the low byte buffer into the timer 0 preload register (16-bit). The Timer 0 preload register is changed by writing TMR0H operations and writing TMR0L will keep the Timer 0 preload register unchanged. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid any false timing problem. Reading TMR0L returns the contents of the low byte buffer. In this case, the low byte of the timer counter 0 cannot be read directly. It must read the TMR0H first to make the low byte contents of the Timer 0 be latched into the buffer. The TMR0C is the Timer 0 control register, which defines the Timer 0 options. The timer counter control registers define the operating mode, counting enable or disable and active edge. Register Label 3/4 3/4 TMR0C (0EH) TON 3/4 TM0 TM1 Bits 0~2 3 4 5 6 7 R/W RO 3/4 RW 3/4 RW
Unused bit, read as 0 Unused bit, read as 0 Enable/disable the timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Fixed bit 7, 6=10, internal timer mode
Register
Label 3/4 TON
Bits 0~3 4 5 6 7
R/W 3/4 RW 3/4 RW Unused bit, read as 0
Function
Enable/disable the timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Fixed bit 7, 6=10, internal timer mode
TMR2C (2AH)
3/4 TM0 TM1
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TMR2L will keep the timer 2 preload register unchanged. Reading TMR2H will also latch the TMR2L into the low byte buffer to avoid any false timing problem. Reading TMR2L returns the contents of the low byte buffer. In other words, the low byte of the timer counter 2 cannot be read directly. It must read the TMR2H first to make the low byte contents of Timer 2 be latched into the buffer. The TMR2C is the Timer 2 control register, which defines the Timer 2 options. The timer counter control registers define the operating mode, counting enable or disable and active edge. If the timer counter starts counting, it will count from the current contents in the timer counter to FFFFH. Once an overflow occurs, the counter is reloaded from the timer counter preload register and generates the corresponding interrupt request flag (T2F; bit of INTC0) at the same time. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR2C) should be set to 1. The overflow PFDC Register Label 3/4 TIM2 PFDB PFDC (2FH) PFD PFDB/PWM1 PFD/PWM2 Bits 2~0 3 4 5 6 7 R/W R RW RW RW RW RW Unused bit, read as 0 1: The timer 2 frequency source is 3.58MHz/4 0: The timer 2 frequency source is 32768Hz 1: Enable PFDB 0: Disable PFDB 1: Enable PFD 0: Disable PFD 1: Enable PFDB 0: Enable PWM1 1: Enable PFD 0: Enable PWM2
D a ta B u s T im e r 2 P r e lo a d R e g is te r R e lo a d
of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I can disable the corresponding interrupt service. In the case of timer counter OFF condition, writing data to the timer counter preload register will also reload that data to the timer counter. But if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. The timer counter will still operate until overflow occurs. When the timer counter (reading TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be taken into consideration by the programmer. The Timer 2 can also be used as PFD output by setting PWM1 and PWM2 to be PFD and PFDB output respectively by 2FH.7 and 2FH.6. When the PFD/PFDB function is selected, setting 2FH.4/2FH.5 to 1 will enable the PFD/PFDB output and setting 2FH.4/2FH.5 to 0 will disable the PFD/PFDB output.
Function
T o In te rru p t 3 .5 8 M H z /4 32768H z MUX P F D C .3 T im e r C o u n te r 2 2
O v e r flo w
2 F H .5 PW M 2 dac 2 F H .4 PW M 1 dac 2 F H .6 2 F H .7
PW M2
L o w B y te B u ffe r
PW M1
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HT23B60
RTC & WDT & LCD Clock
* RTC function
Register RTC (24H)
Label 3/4 RTCEN RTCSET
Bits 6,4 ~0 5 7
R/W RO RW RW Unused bit, read as 0
Function
Enable/disable the RTC counting (0: disable; 1: enable) RTC time-out flag (1: active; 0: inactive) dynamically under software control. To function as an input, the corresponding latch of the control register must be written a 1. The pull-high resistance will exhibit automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H. After a chip reset, these input/output lines remain at high levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into t h e C P U , e xe cu t e t h e d e f i n e d o p e r a t i o n s (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device. Port B are share pad, each pin function are defined by mask option, when the PB3 be used as a normal I/O port, INT function must be disable. (Set [0BH].4 to 0). The PB2, PB1 and PB0 share with serial data input, serial data output and serial clock. If the serial function is selected, the related I/O register (PB) cannot be used as general purpose register. Reading the register will result to an unknown state.
The real time clock (RTC) is used to supply a regular internal interrupt. Its time-out period is 2Hz. If the RTC time-out occurs, the interrupt request flag RTCF and the RTCSET flag will be set to 1. The interrupt vector for the RTC is 14H. When the interrupt subroutine is serviced, the interrupt request flag (RTCF) will be cleared to 0, but the flag RTCSET maintain its original value. If RTC is time-out, the flag RTCSET and RTCF will be set to 1. The flag RTCSET can be cleared to 0 by software.
F1
3 2 k H z X 'T A L
1 /1 6 3 8 4 1 /1 6 TON
IN T L C D D r iv e r (2 0 4 8 H z )
Input/Output Ports There are 14 bidirectional input/output lines in the HT23B60, labeled PA and PB, which are mapped to the data memory of [12H], [14H], respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H). For output operation, all data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor (software option 35H, 36H) structures can be reconfigured
D a ta B u s D W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r P u ll- H i C o n tr o l R e g is te r D W r ite I/O
Q CK S
V V
DD
Q
DD
W eak P u ll- u p
Q CK S
PA0~PA7 PB0~PB5
Q
M U X
R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n
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Bit7 1: pull-high 0: No pull Bit6 1: pull-high 0: No pull Bit5 1: pull-high 0: No pull Bit4 1: pull-high 0: No pull Bit3 1: pull-high 0: No pull Bit2 1: pull-high 0: No pull Bit1 1: pull-high 0: No pull Bit0 1: pull-high 0: No pull
PA Pull-High Resistor Bit7~Bit6 Unused bit 0: No pull 0: No pull 0: No pull 0: No pull 0: No pull 0: No pull PB Pull-High Resistor Bit5 1: pull-high Bit4 1: pull-high Bit3 1: pull-high Bit2 1: pull-high Bit1 1: pull-high Bit0 1: pull-high
PWM Interface The HT23B60 provides an 8 bit (bit 7 is a sign bit) PWM D/A interface, which is good for speech synthesis. The user can record or synthesize the sound and digitize it into the program ROM. This sound could be played back in sequence of the functions as designed by the internal program ROM. There are several algorithms that can be used in the HT23B60, namely, PCM, m_LAW, DPCM, ADPCM...etc. The PWM circuit consists of seven counters. When initialized, QB goes high and when an overflow occurs, QB goes low. When the PWM controller bits 0 of the 30H are set as 0, each of the 128 clock will initialize the counter and load the value that come from PWM data buffer to counter. The PWM modulation can be controlled by using a different value of the PWM data buffer. A single bit can control the signal changes from the PWM1 or PWM2 output. The PWM clock source comes from the system clock divided by a 3-bit prescaler. Setting data to P0, P1 and P2 (bit3, 4, 5 of 30H) can yield various clock sources. Setting PWM controller bits D0, D1 (bit6, 7 of 30H) can control the interrupt as to how many times the counter overflows. BZ/SP 0 0 1 1 Note: 6/7 Bit 0 1 0 1 F1 F0 F0 F0 F0 F2 (Sampling Rate) F0/64 F0/128 F0/64 F0/128 Device 32 speakers 32 speakers Buzzer/ 8 speakers Buzzer/ 8 speakers
On the sampling rate table, we can easily see that the sampling rate is dependent on the system clock. If start bit of the 30H.0 is set as 1, the PWM2 and PWM1 will output a GND level voltage. Label Bits PWM Dis/En BZ/SP 6/7 Bits 0 1 2 Function Enable/disable PWM output 0: enable; 1: disable Output driver select 1: buzzer; 0: speaker PWM counter bit select 1: 7 bits; 0: 6 bits 3 bits preload counter Bit5~3: 000B~111B (0~7); Bit3: LSB
P0~P2 3~5
D0, D1 6, 7 PWMI D1 0 0 1 1 D0 0 1 0 1 PWM Interrupt 1 2 4 8
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 7-bit 6-bit Note: D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 X
X stands for dont care Bit7: Sign bit
F1: for PWM modulation clock and F2 for sampling clock F0: system/[n+1], n=0~7 (n: 3 bits preload counter) X stands for dont care
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HT23B60
F0
S ta r t B it L a tc h F1 F2 O n e S a m p lin g T im e 1 2 8 C lo c k
PWM
D a ta B u s P W M D a ta B u ffe r (3 1 H ) V F1
S y s te m
C lo c k
P r e s c a le r F0
DD
S ta r t B it 3 0 H .0 PW MI F2
D iv .
CK PE
7 B its C o u n te r O v e r flo w
D CK
Q Q
R
P W M D A C 1 fo r 3 2 W
SPK
P W M D A C 2 fo r 3 2 W
SPK
30H.1=0 Speaker
D a ta B u s P W M D a ta B u ffe r (3 1 H ) V F1
S y s te m
C lo c k
P r e s c a le r F0
DD
S ta r t B it PW MI F2
D iv .
CK PE
7 B its C o u n te r O v e r flo w
D CK Q R
Q
S ig n b it P W M D A C 1 fo r B Z P W M D A C 2 fo r B Z
30H.1=1 Buzzer
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Serial Interface Protocol (SPI) 3 wire SPI format, support 32KBytes/64KBytes /128K.Bytes/256KBytes Rising edge latch data, falling edge output data Serial RAM Control Register Register Label 3/4 Busy 3/4 SRC (32H) Sread W/R SMODE Sclk0 Sclk1 Sclk1 0 0 1 1 Bits 0 1 2 3 4 5 6 7 Sclk0 0 1 1 1 Unused bit, read as 0 0: The data register is full (readable) or empty (writeable) (Default=0) 1: Serial RAM interface is busy, cannot write/read the data register Unused bit, read as 0 1: Series read; 0: step read W/R=0: read mode; To read data from the external serial RAM W/R=1: write mode; To write data to the external serial RAM SPI mode setting 0: Mode 0; 1: Mode 3 Serial RAM interface clock, Default=0 Serial RAM interface clock, Default=0 Serial RAM interface clock selector Serial RAM interface clock=system clock/2 Serial RAM interface clock=system clock/4 Serial RAM interface clock=system clock/8 Serial RAM interface clock=system clock/16 Function
* Data are read from or written to the Data Register which is transmitted through the Serial RAM interface * After the next 8-bit data are written to, it is transmitted to the 8 Serial RAM interface clock * Within the 8 serial RAM interface clock, while transmission occurs the busy flag goes 1, after which, when the trans-
mission is completed, the busy flag goes 0 Serial RAM Data Register Address Register 33H SRD 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 R/W R/W Default 00000000 (1sb)
SPI Interface Information
* SPI interface connection
DO DI SCK PXn SI SO SCK CS SI PXm SO SCK CS
C o n tr o lle r (M a s te r)
M e m o ry (S la v e )
M e m o ry (S la v e )
Note:
Controller (master): DO/DI/SCK is SPI interface pin, PXn~PXm are generic I/O port. Memory (slave): SI/SO/SCK is SPI interface pin, CS is chip select.
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* SPI register description
The SPI is used two register, one is data register, the other one is control register. And for the data register is used for data transfer/receiver register, the control register is used to control and display the status of the SPI. Control Register Bit Bit7 Bit6 Bit5 Bit4 Read/writ e Mode Setting B4=1 (R)Write B4=0 (R)Read Bit3 Bit2 Bit1 Bit0
SCK Setting
SCK Setting
SPI Mode Setting
SPI Series Read
Reserved
SPI busy
Reserved
B7,B6=0,0(R)SCK=fSYS/2 B7,B6=0,1(R)SCK=fSYS/4 B7,B6=1,0(R)SCK=fSYS/8 B7,B6=1,1(R)SCK=fSYS/1 6
B5=1 (R)Mode3 B5=0 (R)Mode0
B3=1 (R)Series read RO=0 B3=0 (R)Step read
B1=1 (R)Busy, data serial Out. RO=0 B1=0 (R)Ready, can access data.
Note: The SPI mode0 & mode3 is changed by software option.
* Write data into memory (write mode) timing chart (Mode 0)
CS
tC
SS
SCK tS
U
0 1
2 tH
3
O
4
5
6
7
0 1
2
3
4
5
6
7
DI
H i- Z
DO
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Symbol tCSS tSU tHO
Parameter CS Setup Time Data in Setup Time Data in HOLD Time
Min. 0 3/4 3/4
Typ.
Max. 3/4
Unit ns 3/4 3/4
1 2 SCK 1 2 SCK
3/4 3/4
* The following will show how to write data to memory by the way of the flowchart
S ta rt
Se Co Re (x x x
ttin g n tro l g is te r 1xxxx)
S e ttin g PXn ( C h ip S e le c t)
S e ttin g D a ta R e g is te r ( In s tr u c tio n ) C heck B usy?
S e ttin g D a ta R e g is te r (A d d re s s ) C heck B usy?
Se D Re (D
ttin g a ta g is te r a ta ) C heck B usy?
R e s e ttin g PXn ( C h ip S e le c t)
End
Note:
After to write the data register, the serial out is executed automatically, and the busy bit of the SPI will be set to 1, when the serial out is completed, the busy bit of the SPI will be set to 0, and can be readable/writeable in this moment.
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* Read data from memory (read mode) timing chart (Mode 0)
CS tC
SS
SCK tS
U
0 1
2 tH
3
O
4
5
6
7
0 1
2
3
4
5
6
7
DI
H i- Z
B7
B6
B5
B4
B3
B2
B1
B0
DO
B7
B6
B5
B4
B3
B2
B1
B0
Symbol tCSS tSU tHO
Parameter CS Setup Time Data in Setup Time Data in HOLD Time
Min. 0 3/4 3/4
Typ.
Max. 3/4
Unit ns 3/4 3/4
1 2 SCK 1 2 SCK
3/4 3/4
* The following will show how to read data from memory by the way of the flowchart
Se Co Re (x x x ttin g n tro l g is te r 1xxxx) S e ttin g D a ta R e g is te r ( In s tr u c tio n ) C heck B usy? S e ttin g D a ta R e g is te r (A d d re s s ) C heck B usy? Se Co Re (x x x ttin g n tro l g is te r 0xxxx) Se SC Re D n d in g K to c e iv e a ta C heck B usy?
S ta rt
S e ttin g PXn ( C h ip S e le c t)
R e s e ttin g PXn ( C h ip S e le c t)
End
Low Voltage Detected The Controller provides a circuit that detects the VLCD pin voltage level. To enable this detection function, the LVEN should be written as 1. Once this function is enabled, the detection circuit needs 100ms to be stable. After that, user could read the result from the LVFG. The low voltage detect function will consume power. For power saving, write 0 to LVEN if the low voltage detection function is unnecessary. The tolerance value for the 3 Conditions (Min, Typ. Max) are within 5%.
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Keyscan LCD out port structure
D a ta B u s D CK Q S 0 S e g _ o C o n tr o l R e g is te r C h ip R e s e t LCD SEG 0~15 D a ta B u s Q
M U
1
D CK S Q
Q
X
SEG 0~SEG 15
W r ite I/O C h ip R e s e t
4 6 .5 4 H z 1 1024H z 2 3 4 5 6 7 8 9 10 11 1 2 3 4 11
COM0
V DD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND V DD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND In t F re q u e n c e 9 3 H z <250ms In t, C le a T u rn T u rn In p u T u rn T u rn T u rn T u rn In p u T u rn T u rn rLC on on tPA o ff o ff on on tPA o ff o ff D o u tp u t P C & P D P A P u ll- H i R e s is te r L C D o u tp u t P C LC PA PA LC D o u tp P u ll- H P u ll- H D o u tp ut iR iR ut PC e s is te r e s is te r PD <250ms
SEG0
L C D o u tp u t P D P A P u ll- H i R e s is te r
R e tu rn In t.
For every Frame, each have a Common signal, all of which can generate a single interrupt. The Scan Key performs the following:
* The keyscan loop with 32kHz system frequency * The keyscan loop executes every 2 keyscan Int,. * After an Interrupt occurs, clear LCD segment output port * Turn on the PA Ports Pull-hi resistance * Turn on the LCD segment output port. * Use the LCD segment Output port and input port PA to implement the Key Scan * Take the Scan value and store into the Memory * Turn off the LCD segment output port transition to LCD segment output. * Turn off the PA pull-hi * Return to the main routine and change system frequency * The keyscan function have to be completed in the period of interrupt time. * The keyscan function is generated by common signal. When the LCD function is enable, the keyscan function can be
used.
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Example: ;*keyscan loop executes every 2 keyscan Int. clr clr set clr mov set clr cpla sz jmp set clr mov set clr cpla sz jmp reti lcdpc lcdpd paphc lcdpcc a,pa lcdpcc paphc acc acc speed_up paphc lcdpdc a,pa lcdpdc paphc acc acc speed_up ;clear LCD output (seg0~seg7) ;clear LCD output (seg8~seg15) ;enable PA Pull-hi ;seg0~seg7 output port ;write PA to ACC ;turn on seg0~seg7 ;disable PA Pull-hi ;complement ACC ;check if stroke down ;then change from Normal mode to Green mode ;enable PA Pull-hi ;seg8~seg15 output port ;write PA to ACC ;turn on seg8~seg15 ;disable PA Pull-hi ;complement ACC ;check if stroke down ;then change from Normal mode to Green mode
LCD output control (38H) Bit7 1: seg7 0: output Bit6 1: seg6 0: output Bit5 1: seg5 0: output Bit4 1: seg4 0: output Bit3 1: seg3 0: output Bit2 1: seg2 0: output Bit1 1: seg1 0: output Bit0 1: seg0 0: output
LCD output (37H) Bit7 D7 Bit6 D6 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 (Seg0) D0
LCD output control (3AH) Bit7 1: seg15 0: output Bit6 1: seg14 0: output Bit5 1: seg13 0: output Bit4 1: seg12 0: output Bit3 1: seg11 0: output Bit2 1: seg10 0: output Bit1 1: seg9 0: output Bit0 1: seg8 0: output
LCD output (39H) Bit7 D7 Bit6 D2 Bit5 D5 Bit4 D4 Bit3 D3 Bit2 D2 Bit1 D1 Bit0 (Seg8) D7
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Mask Option The following table shows many kinds of mask option in the Databank Controller. All these options should be defined in order to ensure prober system functions Name Mask Option WDT source selection RC(R)Select the WDT OSC to be the WDT source T1(R)Select the instruction clock to be the WDT source 32kHz(R)Select the external 32768Hz to be the WDT source Disable(R)Disable the WDT function This option defines how to clear the WDT by instruction One clear instruction(R)The CLR WDT can clear the WDT Two clear instructions(R)Only when both of the CLR WDT1 and CLR WDT2 have been executed, then the WDT can be cleared HALT function selection Defines the HALT function either disabled or enabled Port A wake-up selection. Defines the wake-up function activity All port A have the capability to wake-up the chip from HALT This wake-up function is selected per bit
WDT
WDTinstr
HALT option
Wake-up PA
This option describes the LCD bias current. There are three types of selection *_Selectable as small, middle or large current LCD bias register selection Small current: 660K Middle current: 330K Large current: 66K PB0~2 share pad option LCD duty option LCD bias option PB3 share pad option Defines the pad PB0~PB2 whether normal I/O pad or serial RAM interface pad Defines the LCD duty whether 1/10 or 1/11 duty Defines the LCD bias whether 1/4 or 1/5 bias Defines the pad PB3 whether INT interrupt input pad or normal I/O pad
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Application Circuits
15kW 50nF 3nF XC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB5 PB4 PB3 D I/ PB2 DO / SCLK/ PB1 PB0
32768H z
V
DD
R1 VLCD VDD L B IN
R2
X IN
XOUT
SEG0 SEG 59 L C D D is p la y
H T23B 60
COM0 CO M 10 PW M1 PW M2
60 Segm ent 11 C om m on
PA0
Seg0 Seg1 Seg2
SRAM
Seg13 Seg14 Seg15
PA1 PA2 PA3 PA4 PA5
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.10
48
March 1, 2004
HT23B60
Package Information
100-pin QFP (1420) Outline Dimensions
C D 80 51 G H
I 81 50
F A B
E
100
31 K 1 30 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.10
49
March 1, 2004
HT23B60
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2004 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
50
March 1, 2004

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